The big picture: Nvidia lifted the embargo on its Vera CPU deep dive this week, and the disclosure amounts to a direct challenge to two decades of x86 datacenter design philosophy. This is the most detail the company has shared on the chip since it first appeared on the Rubin roadmap, and it confirms something I have suspected for a while: Nvidia is not treating the CPU as an attach story anymore. It is treating it as a battleground with a lot of potential dollars at play.
Vera is built around the Olympus core, the first custom CPU core Nvidia has ever brought to the datacenter and the first custom core the company has designed anywhere since the Denver and Carmel efforts of the Tegra era nearly a decade ago.
Ryan Shrout is a longtime technology analyst and industry veteran who has spent over two decades covering PC hardware, graphics, and semiconductors. He previously led technical marketing at Intel and was the founding editor of PC Perspective. He is currently President and GM at Signal65. You can follow him on X @ryanshrout.
Grace used licensed off-the-shelf Arm Neoverse V2 cores. Olympus is an Nvidia design from the ground up, a wide, high-IPC core with a 10-wide decode front end that reorders aggressively and prefetches based on patterns like graph structures in memory.
88 of those cores sit on a monolithic compute die, running 176 threads through a partitioned scheme Nvidia calls Spatial Multithreading, a deliberate departure from the opportunistic resource sharing of traditional SMT.
That monolithic choice matters. Nvidia still uses chiplets for the memory controllers and I/O, but the compute die is one piece of silicon connected by a second-generation scalable coherency fabric. The company measures bisection bandwidth across the die at roughly 3.4 terabytes per second.
The memory subsystem is LPDDR5X hardened for the datacenter with ECC and full telemetry, delivering up to 1.2 TB/s of bandwidth, roughly 3x the memory bandwidth per core and about 5x the bandwidth per watt of conventional DDR-based server designs (all based on Nvidia claims).
The headline claims stack up as roughly 2x faster performance from the Olympus core, 3x the core-to-core bandwidth of chiplet-based competition, and 40% lower memory latency under load through the LPDDR5X subsystem.
Vera ships in two forms: a dense liquid-cooled rack packing 256 CPUs and more than 22,000 cores, and a conventional air-cooled 2U with two sockets. Dell has committed to multiple PowerEdge systems built on it. Nvidia sizes the opportunity as a $200 billion expansion of the CPU market, which explains a lot of the recent market dynamics.
The argument behind the architecture
In 2014, a top Xeon carried 14 to 18 cores. Today an Epyc Turin part carries 128. Core counts grew roughly 9x over that stretch because cloud economics rewarded rentable vCPUs, while per-core performance only about doubled. Chiplets kept costs down but taxed memory bandwidth, data movement, and latency along the way.
Nvidia argues that agentic AI breaks this trade. An agent reasons on the GPU, then drops to the CPU for tool calls, SQL queries, API work, and scripting, then goes back to the GPU, sometimes hundreds of times per task. That loop is sequential.
You cannot throw more cores at a sequential loop and make it shorter. Only a faster core, fed with data faster, compresses it. The loaded-latency data Nvidia showed makes the point visually, with chiplet designs hitting a saturation wall just shy of 400 GB/s of memory traffic while Vera keeps scaling.
The company has landed on “max single-threaded CPU at scale” as the category name. It is a mouthful, and I will get to that.
The proof points
The customer data is early but notable. Perplexity ran coding sandboxes on Vera and completed jobs 1.5x faster than the production Xeon fleet it runs today, with concurrent sandbox startup 1.9x faster.
The New York Stock Exchange, which processes 1.1 trillion records a day, tested Vera with the Redpanda streaming engine on HPE systems and measured 6x lower p99 latency versus Epyc Turin, and is now evaluating it as a replacement. Los Alamos National Laboratory saw 7x on an agentic workload and 3x on radiation transport and multigrid simulation codes.
These are real workloads rather than synthetic benchmarks, which I give Nvidia credit for, and the supporting documentation puts names and configurations on most baselines. They remain vendor-supplied and worth reading closely.
The SPEC CPU 2026 numbers carry an estimated label from a pre-production reference system, and every comparison lands on Zen 5 Turin or current and older Intel silicon. The Los Alamos runs were measured against a Sapphire Rapids based supercomputer that launched in early 2023. Beating shipping parts is the right first test, but Venice and Diamond Rapids arrive within the year, and that is the fight that will settle this.
Where there is more detail needed
I asked the Nvidia team directly during the analyst briefing last week what actually separates an agentic CPU from a plain, very good datacenter CPU. We have had big, fast processors running back-to-back loops of VMs and containers for years. Is this genuinely a new workload class, or a fast CPU wearing new marketing?
To their credit, the team acknowledged that “agentic CPU” is the wrong label and would pigeonhole the part. The honest answer is that the fundamentals have not changed, but the rates have.
Agent pipelines hydrate and tear down environments constantly rather than occasionally. Memory pressure is continuous. Latency under load becomes the whole game, because every millisecond the CPU stalls is a millisecond a very expensive GPU sits idle. That is a real architectural argument, and the decision to spend die area on per-core speed instead of core count is a genuine philosophical break from where x86 roadmaps have been heading.
What the market needs now is independent, rigorous CPU measurement built around these agentic pipelines, run across current and next generation parts from every vendor. That is exactly the kind of work we are looking forward to diving into at Signal65.
The ecosystem arrived on day one, to no surprise
The partner roster attached to this launch is unusually deep for a CPU announcement. OpenAI says it will deploy Vera at scale beginning in Q3, and the early adopter list also includes Anthropic, SpaceX, and Perplexity, with Los Alamos, NERSC, and TACC representing the supercomputing side.
Dell, HPE, Lenovo, Supermicro, and Bull all have Vera systems coming, backed by the full ODM bench.
The rack-scale platform is ramping just as visibly. CoreWeave was the first cloud to bring up and validate Vera Rubin NVL72 and published the first measured numbers from live hardware, a 10x gain in tokens per second per megawatt over Grace Blackwell NVL72 on DeepSeek-R1.
Google Cloud stood up the first A5X instance on Vera Rubin for the reinforcement learning startup Ineffable Intelligence, Azure and OCI have racks running, and a newly expanded Microsoft and Mistral agreement puts Vera Rubin at the center of a multibillion-dollar European buildout.
On the CPU specifically, DeepInfra, which serves nearly five trillion tokens a week, measured support for 1.6x more concurrent agents and 2.2x faster orchestration versus Granite Rapids. Nvidia counts 300 partners and more than 350 factory sites in 30 countries behind the ramp.
What this means for AMD, Intel, and the hyperscalers
The timing is not subtle. This disclosure lands the day before Advancing AI opens in San Francisco, the flagship AMD event where the 256-core Zen 6 Venice generation of Epyc and the Instinct MI450 family are expected to headline the keynote from Lisa Su on Thursday. Nvidia just set the terms of the datacenter CPU conversation roughly 24 hours before its biggest rival takes the stage.
If a faster CPU returns GPUs to work sooner, the CPU price becomes a rounding error in rack TCO, and the fight shifts from dollars per core to tokens per rack. That framing is the one AMD and Intel now have to answer, and it is a very different conversation than the one that produced 128-core roadmaps.
AMD is not conceding the frame. It has already argued that rack-level performance per watt favors high-core-count Epyc, and the 256-core Venice generation will sharpen that response. Intel has Diamond Rapids coming. The hyperscalers have Graviton, Axion, and Cobalt, all designed around the scale-out economics Vera explicitly rejects.
But Nvidia is not selling a merchant CPU into a commodity socket. It is selling the CPU as the utilization lever for the most expensive assets in the AI factory. If a faster CPU returns GPUs to work sooner, the CPU price becomes a rounding error in rack TCO, and the fight shifts from dollars per core to tokens per rack.
That framing is the one AMD and Intel now have to answer, and it is a very different conversation than the one that produced 128-core roadmaps.
Nvidia has promised deeper head-to-head benchmark data against both x86 and Arm competition in the coming weeks. That data, and the independent validation that should follow it, will tell us whether Vera resets the datacenter CPU conversation or simply carves out a well-defended niche inside the Nvidia rack.
